Industrial Talks and Tutorials
Industrial Talks (November 12, Monday, 2018)
[Industrial Talk 1] (13:00~14:00)
Arm Cortex CPU cores and technology portfolio
Senior FAE Manager, ARM, Korea
[Industrial Talk 2] (14:00~15:00)
Efficient inference and training of deep neural networks in limited precision
Jun Haeng Lee
Research Master at Samsung Advanced Institute of Technology (SAIT), Korea
[Industrial Talk 3] (15:00~16:00)
Memory Subsystem design for Consumer Electronics
Ken Kyuseok Cho
DDR PHY Professional, MID Team, SIC Center, CTO, LG Electronics, Korea
Ken Kyuseok Cho has been working on high performance and low power memory interfacing IP design for SoC, memory circuit design engineering since 1995. Experienced deep sub-micron CMOS technology including 16/14/12/10nm finfet technology, full custom analog-digital mixed signal designs and ASIC FE/BE design flows. Before joining LG Electronics as an IP design engineer, he worked as DRAM circuit designer and program manager for 18 years in several major DRAM companies in 3 continents. Ken Kyuseok Cho holds B.S. in ECE and M.S. in Semiconductor Engineering from Korea University.
Tutorials (November 12, Monday, 2018)
[Tutorial 1] (16:15~17:45)
AI Processor with Nano Core-In-Memory Architecture for Function-Safe Autonomous Driving
Group Leader, AI Processor Research Group, Electronics and Telecommunications Research Institute (ETRI), Korea
Youngsu Kwon received B.S., M.S., and Ph.D. degrees from Korea Advanced Institute of Science and Technology (KAIST), Republic of Korea at 1997, 1999, and 2004, respectively. He had been with Microsystems Technology Laboratory (MTL), Massachusetts Institute of Technology as a Postdoctoral Associate from 2004 to 2005 for designing 3-Dimensional FPGA. He is now Group Leader of AI Processor Research Group, Intelligent SoC Research Department, Electronics and Telecommunications Research Institute (ETRI), Republic of Korea since 2005. In ETRI, he is leading the design of Korean AI Processor, Aldebaran. He has authored over 30 internal journal and conference papers with special interest in low-power processor core design, many-core architecture, CAD and algorithmic optimizations of circuits and systems. He received Government Recognition Award for Science and Technology in 2016, Excellent Researcher Award from Korea Research Council in 2013, Industrial Contributor Award from Korean Federation of SMEs in 2013, and medals from Samsung Humantech Thesis Prize. The Aldebaran CPU core and Application processor for which he acts as a leading architect received the Presidential Award of Korean Semiconductor Design Competition in 2016.
[Tutorial 2] (16:15~17:45)
Benchmarking Advanced CMOS and Beyond-CMOS Technologies
Research Professor, Department of Electrical and Computer Engineering, The University of Texas at Dallas, USA
Dr. Andrew Marshall is a research professor at the University of Texas at Dallas, where he specializes in advanced CMOS, Analog Security and beyond CMOS benchmarking. He was with Texas Instruments for 27 years, leading teams developing high voltage and current devices, analog IC design, and power integrated circuits, at technology nodes from 10µm to 20nm. Dr. Marshall also worked on benchmarking of semiconductors IC processes, including performance characteristics of MOS and passive devices. During this time he attained the Texas Instruments Fellow (TI Fellow) technical rank.
He has authored or co-authored over 100 papers in conferences, peer reviewed journals and proceedings, and holds 85 issued patents. Dr. Marshall is a Fellow of the United Kingdom Institute of Physics, and a Fellow of the IEEE.
Short Tutorials (November 14, Wednesday, 2018)
[Short Tutorial 1] (10:45~11:30)
Basics of Jitter Analysis
Professor, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Korea
[Short Tutorial 2] (11:30~12:15)
Minimum-Energy-Driven Integrated Circuits Design for Green Electronics
Tony Tae-Hyoung Kim
Associate Professor, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore